Pure-Play Semiconductor Foundry Business Model: How It Makes Money
Direct answer: A pure-play semiconductor foundry earns revenue per wafer manufactured for fabless customers, with pricing that varies by process node advancement, wafer size, and committed volume. The business is capital-intensive and process-leadership-dependent: foundries that maintain the leading-edge node attract the most valuable customers and the highest wafer prices, while those that fall behind serve lower-margin commodity markets. TSMC is the dominant example, with more than 50% market share at advanced nodes.
What a pure-play foundry does
A pure-play foundry manufactures semiconductor chips for companies that own the chip IP but do not operate their own fabrication facilities. The customer provides design files; the foundry manufactures wafers using its own process technology, tests for yield, and ships the finished wafers or diced chips back to the customer. The foundry does not compete with its customers: it has no chip IP, no products to sell end users, and no interest in the downstream markets its customers serve. This neutrality is a structural feature of the pure-play model and a reason why major fabless companies concentrate their advanced-node volumes at TSMC rather than at Samsung Foundry, which also has its own chip products in direct competition with Samsung's foundry customers.
Revenue structure
Revenue is priced per wafer (a silicon wafer on which hundreds or thousands of chips are simultaneously fabricated). Leading-edge process nodes (3nm, 5nm, 7nm) command significantly higher wafer prices than mature nodes (28nm, 40nm, 90nm) because of the equipment investment and manufacturing complexity required. Volume commitments typically secure lower per-wafer pricing; spot orders command a premium. Long-term supply agreements (LTAs) guarantee a customer a defined wafer allocation over 2 to 5 years in exchange for non-cancellable volume commitments, which improves foundry revenue predictability but transfers utilization risk partially to customers.
Capital intensity and process leadership
A new leading-edge fab requires $15 to $25 billion or more to construct and equip, before a single revenue-generating wafer is produced. Equipment costs dominate: EUV (extreme ultraviolet) lithography machines from ASML cost approximately $150 to $200 million each, and a leading-edge fab requires dozens. The capital investment must be committed years before the fab is operational, and the investment decision is made before the full demand picture for the node is known. This creates significant investment risk: a foundry that misreads demand or loses key customers on a new node may fail to fully utilize an expensive facility.
Process leadership is the primary competitive dimension for attracting leading-edge volume. Chip designers who require the most advanced node go to whichever foundry offers it most reliably at commercial yield. TSMC's sustained leadership in process node advancement since the late 1990s has produced compounding customer concentration: the largest fabless chip companies that require leading-edge fabrication have limited alternatives, which gives TSMC pricing power on leading-edge wafers.
Utilization and yield
Utilization (the fraction of fab capacity that is producing wafers) directly affects profitability because operating costs (labor, chemicals, energy, equipment maintenance) continue regardless of wafer volume. A fab running at 60% utilization has significantly higher unit costs than the same fab at 90% utilization. Utilization falls during demand downturns when customers reduce orders, and this operating leverage amplifies the earnings impact of a demand cycle downturn. Wafer yield (the fraction of chips on each wafer that pass testing) similarly affects unit economics: lower yield means fewer saleable chips per wafer, increasing effective cost per chip.
Failure modes
Falling behind on process node advancement causes customer defection to more capable foundries and loss of the high-value leading-edge segment. Underutilization during demand downturns dramatically increases unit costs and compresses margins. Geopolitical risk at the concentration of advanced capacity in Taiwan creates supply chain vulnerability for global customers. Customer concentration means losing a major customer (Apple, NVIDIA) has a disproportionate revenue impact. Equipment supply constraints, particularly for advanced lithography tools, can delay new node readiness.
Related models
- Fabless Semiconductor Designer: the customer whose chips the foundry manufactures
- Semiconductor Equipment Manufacturer: supplies the tools foundries require to operate
Frequently Asked Questions
How does a pure-play semiconductor foundry make money?
A pure-play semiconductor foundry earns revenue by manufacturing wafers to the specifications provided by its fabless customers. Revenue is priced per wafer, with the price varying by process node, substrate size, and volume committed. The foundry does not own the chip IP; it manufactures chips according to the customer's design files using its own process technology. Gross margin depends on the spread between wafer revenue and the cost of materials, process chemicals, equipment depreciation, labor, utilities, and yield losses.
Why is process leadership critical for a semiconductor foundry?
The most advanced process nodes allow chip designers to achieve more performance and better energy efficiency per chip area than older nodes. Fabless customers designing competitive chips for AI, mobile, and high-performance computing require access to the most advanced nodes. A foundry that leads on process node advancement wins the most valuable customers and highest-value wafer pricing. A foundry that falls behind the leading edge can still serve commodity markets, but loses the high-margin, high-growth segments to more capable competitors.
What are the main costs in a semiconductor foundry?
Capital expenditure is the dominant cost: a new leading-edge fab requires $15 to $25 billion or more to build and equip. Ongoing capital expenditure for equipment upgrades and new process node development is continuous. Operating costs include chemicals and materials, energy (semiconductor fabs are among the most energy-intensive industrial facilities), labor for a highly skilled technical workforce, and equipment maintenance. Depreciation of the equipment fleet is a major non-cash cost flowing through the income statement.
What is wafer yield and how does it affect foundry economics?
Wafer yield is the percentage of chips on a wafer that pass quality and function testing. A wafer with 100% yield means every chip produced functions correctly; in practice, imperfections and process variation produce some defective chips on every wafer. Lower yield means fewer saleable chips per wafer, increasing the effective cost per good chip. Yield is highest on mature, well-characterized process nodes and lowest on newly introduced nodes where the manufacturing process has not yet been fully optimized.
What risks does a pure-play foundry face?
The primary risks are: customer concentration (a small number of large fabless customers represent a significant fraction of leading-edge revenue); geopolitical risk from the concentration of advanced capacity in Taiwan; capital cycle risk (multi-billion dollar investment in a new process node must be committed before demand is certain); equipment supply risk from a small number of critical equipment suppliers; and utilization risk during demand downturns, since fab operating costs continue regardless of wafer volume.