Semiconductor Supply Chain
Direct answer: The semiconductor supply chain spans eleven stages from silicon and specialty gases through electronic design automation (EDA) software, intellectual property cores, fabrication equipment, wafer foundries, chip design, advanced packaging, memory production, component distribution, and final end-use applications. ASML holds a global monopoly on the extreme ultraviolet (EUV) lithography equipment required for sub-7nm chips, making it the single most critical chokepoint in the entire chain. TSMC fabricates more than 60% of all logic chips by foundry revenue and more than 90% of sub-3nm volume, creating a second critical concentration point in Taiwan.
How the semiconductor supply chain works
A semiconductor chip is a slice of crystalline silicon, typically 200mm or 300mm in diameter (the wafer), on which billions of transistors are etched using a series of photographic, chemical, and plasma processes. The finished chip is then packaged in a ceramic or plastic housing and tested before shipping to electronics manufacturers. The entire process from raw silicon to packaged chip typically spans 3 to 6 months and involves components, chemicals, and equipment from dozens of specialized companies across multiple countries.
The supply chain has a distinctive structure: some stages are highly concentrated (ASML in EUV equipment, TSMC in advanced foundry, Cadence and Synopsys in EDA), while others have multiple competitors. The concentration points tend to be where the most technical complexity and the longest R&D investment timelines are required, creating durable competitive moats that have persisted through multiple industry cycles.
The dominant commercial model has shifted over the past three decades from vertically integrated "IDM" companies that design and make their own chips, toward a specialized structure in which fabless companies design chips without owning any manufacturing equipment, and contract foundries fabricate them. NVIDIA, AMD, Qualcomm, and Broadcom are prominent examples of fabless companies. TSMC, Samsung Semiconductor, and GlobalFoundries are contract foundries. Texas Instruments and Intel are traditional IDMs that retain their own fab operations.
Semiconductor supply chain stages: key companies and tickers
| Stage | What happens | Key public companies | Tickers |
|---|---|---|---|
| 1. Raw materials | Silicon wafers, specialty gases, photoresists, and process chemicals are produced | Shin-Etsu Chemical, Sumco, Siltronic, Air Products, Linde, Air Liquide | SHECY, SUOPY, WAF.DE, APD, LIN, AIQUY |
| 2. EDA software | Engineers use chip design automation software to design transistor layouts and verify function | Cadence Design Systems, Synopsys | CDNS, SNPS |
| 3. IP cores | Licensed processor architecture building blocks are incorporated into chip designs | Arm Holdings | ARM |
| 4. Capital equipment | Lithography, deposition, etch, inspection, and test equipment is manufactured and sold to foundries | ASML, Applied Materials, Lam Research, KLA Corporation, Tokyo Electron, Teradyne, Advantest | ASML, AMAT, LRCX, KLAC, TOELY, TER, ATEYY |
| 5. Wafer fabrication (foundries) | Chip designs are printed onto silicon wafers using hundreds of process steps | TSMC, Samsung (foundry), Intel Foundry, GlobalFoundries, UMC | TSM, SSNLF, INTC, GFS, UMC |
| 6. Fabless chip designers | Chip companies design silicon without owning fabs, outsourcing manufacturing to foundries | NVIDIA, AMD, Qualcomm, Broadcom, Marvell | NVDA, AMD, QCOM, AVGO, MRVL |
| 7. IDMs (Integrated Device Manufacturers) | Companies design and manufacture chips in their own fabs | Intel, Texas Instruments, Analog Devices, Microchip Technology | INTC, TXN, ADI, MCHP |
| 8. Advanced packaging | Finished dies are assembled into packages; advanced formats stack multiple chiplets together | ASE Technology, Amkor Technology, Intel (for own chips) | ASX, AMKR, INTC |
| 9. Memory | DRAM, NAND flash, and HBM memory chips are manufactured at dedicated fabs | Micron Technology, SK Hynix, Samsung | MU, 000660.KS, SSNLF |
| 10. Distribution | Components are warehoused and sold to electronics manufacturers globally | Arrow Electronics, Avnet | ARW, AVT |
| 11. End applications | Chips are deployed in AI/data center, mobile, automotive, and industrial applications | NVIDIA (AI/GPU), Intel and AMD (CPUs), Apple and Qualcomm (mobile), Infineon and NXP (automotive) | NVDA, INTC, AMD, AAPL, QCOM, IFNNY, NXPI |
Stage 1: Raw materials
Semiconductor fabrication requires extraordinarily pure materials. Silicon wafers must be essentially defect-free at the atomic level. Process gases must contain parts-per-billion concentrations of contaminants at most. Photoresists must expose and develop with nanometer precision.
Silicon wafers are the physical substrate on which all logic and memory chips are built. The dominant suppliers are Shin-Etsu Chemical (SHECY), which holds approximately 30% of the global wafer market, and Sumco (SUOPY), which holds approximately 25%. Siltronic (WAF.DE, listed in Germany) is a third major producer. These three Japanese and German companies supply the silicon starting material for virtually every chip made anywhere in the world.
Specialty process gases are consumed during deposition and etch steps. Nitrogen trifluoride (NF3), fluorine, argon, and other high-purity gases are produced by Air Products (APD), Linde (LIN), and Air Liquide (AIQUY). The concentration in this segment is moderate, but supply disruptions have caused fab slowdowns in past shortage events.
Photoresists and chemicals are the light-sensitive materials used in lithography steps. JSR Corporation (4185.T, Tokyo) and Shin-Etsu Chemical are major photoresist producers. Advanced EUV photoresists are technically demanding products with very few qualified suppliers.
Stage 2: Electronic design automation (EDA) software
Before a single wafer is processed, chip designers spend months or years creating a chip's circuit layout using EDA software. EDA tools simulate transistor behavior, verify that a design will function correctly, optimize for power and performance, and generate the data files that lithography machines use to print the circuit. Without EDA software, modern chip design is impossible.
Cadence Design Systems (CDNS) and Synopsys (SNPS) hold a duopoly in full-flow EDA. Together they account for approximately 70-75% of the global EDA market. Switching costs are extremely high: a chip design team's entire workflow, verification library, and institutional knowledge are embedded in one vendor's toolset. Chip designers do not switch EDA vendors without compelling reason and significant disruption cost. This creates durable pricing power and recurring revenue that persists across semiconductor cycles. Both companies earn approximately 30-35% operating margins.
Synopsys acquired Ansys in 2024, expanding its simulation capabilities beyond chip design into broader engineering simulation. The combined entity strengthens Synopsys's position in system-level chip-package-board co-simulation, an increasingly important discipline as AI chip designs push the limits of thermal and signal integrity.
Stage 3: IP cores
Most chip designs incorporate licensed blocks of pre-designed circuit logic rather than building everything from scratch. The most strategically important licensed IP is processor architecture. Arm Holdings (ARM) licenses its processor instruction set architecture (ISA) and physical CPU core designs to virtually every mobile, embedded, and increasingly server chip designer in the world. Apple's A-series chips, Qualcomm's Snapdragon, Amazon's Graviton, and NVIDIA's data center CPUs all incorporate Arm-licensed elements.
RISC-V is an open-source alternative architecture that is gaining adoption in embedded and research settings but has not yet produced a significant investable public company. Its relevance to investors lies primarily in the threat it poses to Arm's long-term pricing power in commodity microcontroller markets.
Stage 4: Semiconductor capital equipment
This is the most structurally concentrated stage in the supply chain below EDA, and it is the stage that most directly determines which chip designs can physically exist.
ASML (ASML) is the only company in the world that manufactures extreme ultraviolet (EUV) lithography systems. EUV uses 13.5 nm wavelength light to print circuit features below 7nm on silicon wafers. A single EUV machine contains over 100,000 components, is roughly the size of a school bus, and costs approximately $150 to $200 million (High-NA EUV machines introduced in 2024 cost approximately $350 million each). ASML sells approximately 40 to 60 EUV systems per year, with multi-year lead times. TSMC, Samsung, and Intel are the only customers. There is no alternative EUV supplier and no competing technology path to sub-7nm production.
Applied Materials (AMAT) is the largest semiconductor equipment company by revenue. It supplies chemical vapor deposition (CVD), physical vapor deposition (PVD), and etch systems used across all process nodes and by all major foundries. AMAT benefits from every new fab build regardless of which node or which foundry wins market share.
Lam Research (LRCX) is the leading supplier of etch and deposition tools, with particular strength in the multi-step processes required for 3D NAND memory manufacturing. Its installed base at memory fabs gives it a large recurring consumables and service revenue stream.
KLA Corporation (KLAC) supplies process control equipment: inspection and metrology tools that identify defects and measure feature dimensions during chip manufacturing. As feature sizes shrink, the number of inspection steps required per wafer increases, making KLA's revenue per unit area of silicon grow with each process node advance.
Teradyne (TER) and Advantest (ATEYY) supply automated test equipment (ATE) used to verify chip function and screen out defects after fabrication. AI chip complexity has increased test times significantly, growing ATE market demand.
Stage 5: Wafer fabrication
Foundries receive chip designs as data files and execute hundreds of process steps to fabricate the chips on silicon wafers. The process involves repeated cycles of deposition, lithography exposure, etch, and clean. A leading-edge chip may require over 1,000 process steps and take three to four months from wafer start to finished die.
TSMC (TSM) holds approximately 60% of global contract foundry revenue and more than 90% of sub-3nm volume as of 2025. Its manufacturing process maturity, yield performance, and decades of accumulated process knowledge give it a structural lead over all competitors. TSMC's N3 (3nm) and N2 (2nm) process nodes are the only commercially available nodes for advanced logic chips from fabless designers like NVIDIA, AMD, and Apple.
Samsung Semiconductor is TSMC's closest competitor but trails on yield and process maturity at leading nodes. It is a subsidiary of Samsung Electronics (SSNLF), making pure-play foundry exposure through Samsung difficult to isolate from its memory, mobile, and consumer electronics businesses.
Intel Foundry (part of Intel, INTC) is building out its contract foundry ambitions under the Intel Foundry Services initiative. Intel's 18A process node is targeted at leading-edge competition with TSMC by 2025 to 2026, supported by US CHIPS Act funding. Intel's success or failure in this effort will significantly affect the long-term competitiveness of the US domestic semiconductor manufacturing base.
GlobalFoundries (GFS) and UMC (UMC) produce chips at mature nodes (28nm and above) where most automotive, industrial, and analog chips are fabricated. Mature-node fabs are less capital-intensive and serve markets that do not require leading-edge performance but do require long production lives, automotive-grade reliability, and supply continuity.
Stage 6: Fabless chip designers
Fabless companies design chips without owning any manufacturing equipment. They contract all fabrication to foundries (primarily TSMC) and all packaging to OSATs (outsourced semiconductor assembly and test companies). The fabless model allows rapid capital-light design iteration but creates concentrated dependency on TSMC's capacity and pricing.
NVIDIA (NVDA) designs GPUs and AI accelerators that are fabricated at TSMC. The H100 and B200 AI training chips are the highest-revenue semiconductor products in history by unit revenue. NVIDIA's AI chip business reached over $100 billion in annual revenue by 2025.
AMD (AMD) designs CPUs, GPUs, and data center accelerators, fabricated at TSMC. AMD has taken significant server CPU market share from Intel by offering higher performance per dollar on TSMC's leading nodes.
Qualcomm (QCOM) designs Snapdragon mobile application processors and 5G modems. It is the dominant merchant chip supplier for Android flagship smartphones.
Broadcom (AVGO) designs networking, storage, and custom AI chips. Its networking ASICs carry much of the traffic inside AI data centers. Its 2023 acquisition of VMware added a substantial software business.
Marvell Technology (MRVL) designs custom silicon for cloud hyperscalers and networking infrastructure.
Stage 7: Integrated Device Manufacturers (IDMs)
IDMs design and manufacture their own chips, maintaining captive fab capacity. This model requires significant ongoing capital expenditure but provides control over process customization, supply timing, and intellectual property security.
Intel (INTC) is the original IDM and remains the world's largest chip company by revenue (though NVIDIA surpassed it by market capitalization by 2023). Intel's x86 CPUs dominate the personal computer and enterprise server markets but have lost significant share in both markets to AMD. Intel's foundry ambitions represent a strategic pivot to become a contract manufacturer for third parties.
Texas Instruments (TXN) is the leading producer of analog and mixed-signal semiconductors, manufactured in its own fabs. Analog chips do not require leading-edge process nodes; TI's strategy of buying and extending the life of older fabs gives it a cost advantage in this segment.
Analog Devices (ADI) and Microchip Technology (MCHP) are the other major US IDMs, serving industrial, automotive, and communications markets with mixed-signal and microcontroller chips manufactured in their own fabs.
Stage 8: Advanced packaging
After fabrication, bare dies (individual chips cut from wafers) are packaged into the housings that are placed on circuit boards. Advanced packaging has become a strategic differentiator as chiplets (multiple smaller dies assembled into a single package) replace monolithic designs for the most complex chips.
NVIDIA's H100 and B200 GPUs use TSMC's CoWoS (Chip on Wafer on Substrate) packaging to connect the GPU die to HBM memory stacks in the same package. This advanced packaging step is as technically demanding as the chip fabrication itself and is a significant constraint on AI chip production volume.
ASE Technology Holding (ASX) and Amkor Technology (AMKR) are the two largest independent OSATs (outsourced semiconductor assembly and test companies). They package chips for fabless companies that do not want to manage packaging in-house. Intel manages its own packaging for its own chips.
Stage 9: Memory
Memory chips (DRAM for volatile working memory, NAND flash for non-volatile storage, and HBM for AI chip high-bandwidth memory) are manufactured at dedicated fabs and sold as commodity-priced components.
Micron Technology (MU) is the only major US-headquartered memory chip maker. It produces DRAM and NAND at fabs in Idaho, Japan, Singapore, and Taiwan. Micron is building a US DRAM fab in New York with CHIPS Act support.
Memory is the most cyclical segment of the semiconductor industry. Supply additions (new fab capacity) take 2 to 3 years to build; demand can shift within months. When supply exceeds demand, memory prices collapse quickly; when demand exceeds supply, prices spike. Micron's earnings have swung from large losses to very high profits within single years.
High-bandwidth memory (HBM) is a premium DRAM format that stacks multiple DRAM dies vertically and connects them to AI chips (NVIDIA H100/B200, AMD MI300) through the CoWoS packaging process. HBM is in tight supply because its production requires both advanced DRAM fabrication and advanced packaging. SK Hynix (000660.KS), Samsung, and Micron are the three HBM producers. SK Hynix entered volume HBM3E production first and captured a dominant share of NVIDIA's HBM supply, lifting its gross margins to record levels in 2024.
Stage 10: Distribution
Semiconductor component distributors warehouse, finance, and deliver chips and other electronic components to electronics manufacturers. Arrow Electronics (ARW) and Avnet (AVT) are the two largest publicly traded distributors. They provide supply chain services including inventory buffering, demand aggregation, and technical support, earning thin margins on large volumes.
Stage 11: End applications
Chips reach end markets across four major segments: AI and data center computing, mobile devices, automotive electronics, and industrial controls. Each has different growth rates, margin profiles, and cyclicality characteristics.
AI and data center: NVIDIA's H100 and B200 GPUs are the defining chips of the current AI investment cycle, processing the matrix multiplications required for large language model training and inference. AMD's MI300 series is the primary competitive alternative. Intel supplies data center CPUs through its Xeon line.
Mobile: Apple (AAPL) and Qualcomm (QCOM) supply the application processors and modems in premium smartphones. MediaTek (2454.TW) dominates mid-range Android devices.
Automotive: Infineon (IFNNY) and NXP Semiconductors (NXPI) are the leading suppliers of automotive-grade microcontrollers, power management chips, and radar processors. Automotive chips require extreme reliability specifications and long production lifetimes relative to consumer chips.
Investment angles
ASML's irreplaceable monopoly. ASML has no competitor in EUV lithography and will not have one for the foreseeable future. The supply chain, physics, and IP complexity of building an EUV machine are so profound that no credible competing program exists. Demand is structurally tied to every new generation of AI and mobile chips. ASML's risk is primarily demand timing (fab investment cycles) rather than competitive displacement.
The fabless model's capital efficiency. NVIDIA, AMD, Qualcomm, and Broadcom collectively generate some of the highest returns on invested capital in the technology sector because they have no fab capex. They pay for wafer capacity as purchased services. Their R&D investment flows into chip design, which has lower capital requirements than fabrication. The risk of this model is concentrated dependency on TSMC's capacity allocation and pricing.
Equipment makers as cycle-insensitive beneficiaries. AMAT, LRCX, KLAC, and ASML benefit from every new fab build regardless of which foundry or chip designer wins. They also have large installed bases that generate recurring service and spare parts revenue. This makes them less correlated to chip pricing cycles than the foundries and chip designers themselves, though they are not immune to fab investment deferral in severe down-cycles.
HBM memory as an AI-specific demand driver. The AI training chip market has created a new premium memory category (HBM) with supply constraints and pricing well above commodity DRAM. SK Hynix's early HBM3E volume leadership and Micron's ramp are the two investable exposure points for this specific demand driver. HBM margins are substantially higher than commodity DRAM margins, and the supply constraint is expected to persist while AI chip production grows faster than HBM capacity can be built.
EDA duopoly pricing power. Cadence (CDNS) and Synopsys (SNPS) earn approximately 30-35% operating margins with highly predictable subscription revenue. The chip design tool market grows with chip complexity, not with chip unit volumes, which insulates these companies from commodity chip pricing cycles. Chip designs have become more complex with each node generation, consistently expanding the value of EDA software.
Concentration and disruption risks
TSMC Taiwan concentration. Over 90% of sub-3nm chip production is in Taiwan. A military conflict or natural disaster affecting TSMC's fabrication facilities would halt production of virtually all AI chips, advanced mobile processors, and high-performance CPUs globally. The US CHIPS Act and TSMC's Arizona facility are partial mitigations over a multi-year horizon; Taiwan remains the near-term concentration point with no practical alternative.
US and Netherlands export controls. The US Department of Commerce has imposed export controls on advanced semiconductor equipment (particularly EUV and some DUV tools from ASML) and EDA software to prevent China from acquiring sub-14nm fabrication capability. The Netherlands has also restricted ASML's EUV shipments to China under US diplomatic pressure. These controls reduce China-related revenue for ASML, AMAT, LRCX, and EDA vendors, but also accelerate Western fab investment by improving the competitive position of TSMC, Samsung, and Intel versus Chinese foundries.
Semiconductor cyclicality. Memory chips (Micron, SK Hynix) are acutely cyclical: gross margins have ranged from deeply negative to over 50% within single market cycles. Capital equipment (AMAT, LRCX) lags the chip cycle by 6 to 18 months, as discussed in the FAQ below. Investors entering either segment need a view on cycle timing, not just on competitive position.
Leading-edge fab concentration cost. Building a leading-edge fab now costs $20 to $30 billion per facility. This capital requirement effectively limits the number of credible leading-edge foundry competitors to TSMC, Samsung, and Intel. New entrants cannot accumulate the capital or the process knowledge at this cost level without government subsidy support, which both the US CHIPS Act and the EU Chips Act are designed to provide.
Japan and Korea wafer concentration. The silicon wafer market is controlled almost entirely by Japanese and Korean companies (Shin-Etsu, Sumco, Siltronic). A disruption to Japanese industrial capacity, though lower probability than a Taiwan scenario, would affect the raw substrate supply for every chip produced globally.
Frequently asked questions
What is ASML's monopoly and why does it matter to investors?
ASML is the only company in the world that manufactures extreme ultraviolet (EUV) lithography machines, which are required to print the circuit patterns needed for chips below 7nm. A single EUV machine costs approximately $150 to $200 million and takes over a year to deliver. TSMC, Samsung, and Intel are ASML's customers and cannot advance to newer process nodes without these machines. This makes ASML one of the most structurally entrenched positions in any supply chain: there is no alternative supplier, no reverse engineering path due to supply chain and IP complexity, and demand grows with every new generation of AI and mobile chips.
What is the difference between fabless and IDM semiconductor companies?
Fabless semiconductor companies (NVIDIA, AMD, Qualcomm, Broadcom) design chips but outsource manufacturing to foundries like TSMC. This model requires no fab capital expenditure and allows rapid design iteration, but creates dependency on foundry capacity and pricing. Integrated Device Manufacturers (IDMs) such as Intel, Texas Instruments, and Analog Devices both design and manufacture chips in their own fabs. IDMs have higher capital intensity but greater control over process customization, timing, and supply security. The trend since 2000 has been toward fabless, but AI chip demand is creating renewed interest in captive capacity.
How does the semiconductor cycle affect equipment makers differently than chipmakers?
Chipmakers (TSMC, Micron) feel demand cycles first: when smartphone or PC demand slows, utilization drops, pricing falls, and earnings compress quickly. Equipment makers (AMAT, LRCX, KLAC, ASML) feel cycles with a 6 to 18 month lag because fab construction and expansion decisions are made before the utilization decline shows up. Equipment order books build during up-cycles and get deferred during down-cycles. This means equipment makers typically turn down later than chipmakers and recover later, making cycle timing analysis more important for equipment than for chip operating companies.