Taiwan Semiconductor Manufacturing Company (TSM): Foundry Research, Process Leadership and SOX Membership

TSMC (TSM) research pages

• TSMC Financials: wafer revenue by node, operating margin, capex and return on equity
• TSMC Earnings: quarterly wafer revenue, utilization rates, guidance and technology platform mix
• TSMC Revenue by Process Node: leading-edge vs. advanced vs. mature node revenue breakdown
• TSMC Capital Expenditure: fab investment history, N2 and A16 buildout costs, geographic expansion spend
• TSMC Valuation: normalized wafer pricing, utilization leverage, Taiwan geopolitical discount
• TSMC History: 1987 founding by Morris Chang, foundry model invention, leading-edge process leadership timeline
• TSMC Geographic Expansion: Arizona Fab 21, Japan Kumamoto, Germany Dresden and diversification rationale
• TSMC Index Membership: SOX, NYSE composite, global ADR index membership

Quick answer

TSMC is the world's largest dedicated semiconductor foundry, manufacturing chips designed by companies including Apple, NVIDIA, AMD, Qualcomm and Broadcom at process nodes ranging from mature (28nm, 40nm) to leading-edge (N3, N2). TSMC does not design its own products. Approximately 90% of the world's most advanced chips are manufactured by TSMC. TSMC is incorporated in Taiwan and trades on NYSE as an ADR (ticker: TSM) and on the Taiwan Stock Exchange (ticker: 2330.TW). TSM is a member of the Philadelphia Semiconductor Index (SOX).

The central research question: Can TSMC preserve technology leadership and pricing power while expanding geographically and funding ever-more-expensive leading-edge fabs?

TSMC's indispensable position comes with four structural tensions investors must weigh. First, it is geographically irreplaceable in Taiwan while that geography carries geopolitical tail risk. Second, its capex intensity grows with every process generation, requiring sustained leading-edge demand to justify the investment. Third, Apple and a handful of hyperscalers account for a disproportionate share of revenue, concentrating customer dependency at the very top of the product pyramid. Fourth, no single competitor can replicate TSMC's process maturity today, but the competitive landscape over a decade is genuinely uncertain. Understanding these tensions is the starting point for any serious analysis of TSM as an investment.

Company at a glance

What TSMC sells: the foundry model

TSMC was founded in 1987 by Morris Chang and pioneered the dedicated foundry model, in which the chip manufacturer does not compete with its customers by designing its own products. This was a radical departure from the integrated device manufacturer (IDM) model where companies like Intel both designed and manufactured chips. The foundry model enabled the fabless chip industry: companies like Qualcomm, Broadcom and later NVIDIA could focus entirely on chip design without the capital burden of owning fabs. TSMC manufactures chips for hundreds of customers across smartphones, PCs, servers, automotive, IoT, aerospace and defense applications. Apple, NVIDIA, AMD, Qualcomm and Broadcom are among the largest customers.

TSMC's competitive advantage centers on process technology leadership. Its N3 (3nm) node is in volume production, delivering chips for Apple's A-series and M-series processors, NVIDIA's Blackwell GPUs and AMD's latest CPUs. N2 (2nm) is entering production, with A16 (incorporating backside power delivery) planned for future advanced applications. Each new process node costs tens of billions of dollars in equipment (primarily ASML EUV lithography systems), facility construction and process development. Leading-edge chips command higher wafer prices (ASP) because they deliver more performance per unit area and enable capabilities not possible on older nodes.

Mature process nodes (28nm, 40nm, 65nm, 90nm and older) account for a meaningful share of TSMC's revenue and are important for automotive, industrial, power management, RF, display driver and microcontroller chips that do not require leading-edge transistor density. These nodes have been depreciated over many years and generate stable, profitable revenue without new capex. Advanced nodes (N5, N4, N7) sit between leading-edge and mature, serving applications that benefit from density and performance improvements over mature nodes but do not require the latest process.

Foundry economics: wafers, utilization and pricing

TSMC's revenue model is based on wafer pricing. Customers pay per wafer processed, with the price depending on the process node (leading-edge nodes command 3-5x or more the price per wafer of mature nodes), the product specifications and volume commitments. Wafer starts per period and the utilization rate of installed capacity are the key operational metrics. When utilization is high, fixed costs are spread across more wafers and gross margins expand. When utilization falls (as during the 2022-2023 semiconductor downturn when customers cut orders to work off inventory), margins compress.

TSMC's pricing power comes from customers' inability to qualify and manufacture at leading-edge nodes elsewhere. Qualifying a new chip at a new foundry takes 12-18 months or more, during which time the chip must be re-verified across millions of parameter combinations. Customers building products around TSMC N3 processes have built their entire chip architecture around TSMC's specific design rules. Switching to Samsung Foundry or Intel Foundry Services is possible in principle but carries significant engineering cost, risk and time, which gives TSMC substantial pricing leverage at leading-edge.

Geographic diversification

Approximately 90% of TSMC's leading-edge manufacturing capacity is in Taiwan. China's stated claim over Taiwan is the primary geopolitical risk facing TSMC investors. In response to customer and government pressure, TSMC has committed to building fabs outside Taiwan. In the United States, Fab 21 in Phoenix, Arizona will manufacture 4nm and 2nm chips. In Japan, the Kumamoto fab (JASM, a joint venture with Sony and Denso) began production at 28nm with plans to expand to 16nm. In Germany, the Dresden fab (ESMC, with Infineon, NXP and Bosch as partners) will focus on 22nm and 28nm for automotive and industrial customers.

Geographic diversification reduces tail risk from Taiwan disruption and satisfies government requirements for domestic chip manufacturing (especially from the U.S. CHIPS Act and the EU Chips Act). However, building fabs outside Taiwan is significantly more expensive than building in Taiwan due to higher labor costs, less developed supply chains, and construction cost differences. TSMC management has acknowledged the cost premium of overseas fabs, which may compress margins at those facilities relative to Taiwan operations. The diversification strategy is a long-term project that will take a decade or more to meaningfully change TSMC's geographic concentration.

Taiwan geopolitical risk

TSMC manufactures approximately 90% of the world's leading-edge chips in Taiwan. Mainland China's stated goal of eventual unification with Taiwan creates a geopolitical tail risk: military conflict, blockade or economic coercion affecting Taiwan would disrupt a significant fraction of global semiconductor supply. The economic consequences of a TSMC disruption would extend well beyond semiconductor markets, affecting every industry that depends on chips. This is precisely why the U.S., Japanese and European governments have provided incentives for TSMC to build overseas fabs.

For investors, Taiwan risk is difficult to price. It is a low-probability but extremely high-impact scenario. The most useful investor framing is to ask whether the discount on TSMC's valuation (relative to what an identical company based in a less geopolitically sensitive location might trade at) is adequate compensation for the tail risk. Geographic diversification reduces but does not eliminate this risk: even if 10-20% of TSMC's capacity were outside Taiwan by the end of this decade, the Taiwan fabs would still account for the majority of leading-edge output. The correct framework is not binary (conflict or no conflict) but a spectrum of scenarios including economic pressure, export restrictions on TSMC's Chinese customers, and slower but persistent geopolitical risk premium.

Key risks

Geographic concentration and geopolitical risk: As described above, approximately 90% of TSMC's leading-edge capacity is in Taiwan. Any military conflict, blockade or forced disruption in Taiwan would remove the majority of the world's advanced chip supply. This is the most consequential tail risk and the reason TSMC trades at a persistent valuation discount relative to the underlying earnings power of the business.

Leading-edge capex escalation: Each new process node is more expensive to equip than the last. N2 fabs require more EUV systems at higher prices per system than N3. If leading-edge chip demand does not grow fast enough to justify the capex, returns on invested capital compress. The escalating investment required to stay at the frontier creates a structural question about whether the financial model remains as attractive as process nodes shrink further.

Customer concentration: Apple accounts for a very large share of TSMC's revenue, estimated at approximately 25% or more. A significant change in Apple's sourcing strategy, chip design philosophy, shift to in-house packaging or volume reduction would directly impact TSMC's top line. The concentration of revenue in a small number of hyperscalers and consumer electronics OEMs is a persistent risk factor.

Competition: Samsung Foundry is the only competitor with EUV capability and volume production at advanced nodes. Intel Foundry Services is investing heavily to become a leading-edge foundry with its own process roadmap. Neither has matched TSMC's yield, efficiency and process maturity at leading-edge nodes, but competitive dynamics over a 5-10 year horizon are genuinely uncertain. A meaningful improvement in Samsung or Intel foundry yields would reduce TSMC's pricing power.

Export restrictions: U.S. restrictions on TSMC's ability to manufacture chips for certain Chinese customers (notably chips with advanced AI capabilities) reduce the addressable customer base. If restrictions tighten further, TSMC's exposure to the Chinese market (which includes a large share of mature-node revenue as well) could be meaningfully impaired.

Currency risk: TSMC reports revenue primarily in U.S. dollars but incurs a significant portion of its costs in New Taiwan dollars. Appreciation of the TWD against the USD compresses margins expressed in USD. This currency exposure is partially managed through hedging but is a persistent earnings variable.

Valuation framework

TSMC is a capital-intensive business where the key financial metrics are revenue per wafer (ASP), gross margin (sensitive to utilization and node mix), operating leverage (high fixed cost structure means utilization swings drive large margin changes), capex as a percentage of revenue, and returns on invested capital. A normalized cycle approach models wafer revenue at mid-cycle utilization, applies a normalized gross margin reflecting the mix of leading-edge, advanced and mature nodes, then deducts capex to arrive at free cash flow. The Taiwan geopolitical risk discount is real and structural: it is not something that disappears with better earnings, and investors should factor it into required return assumptions as a persistent feature of the investment thesis, not a temporary discount to be arbitraged away.

Leading-edge ASP expansion is the primary long-term earnings driver. If TSMC can charge proportionally more for each successive process node while maintaining or improving yields, revenue per wafer grows even without volume increases. The ongoing AI infrastructure buildout (which requires leading-edge TSMC chips for NVIDIA's Blackwell, AMD's Instinct and Apple's Neural Engine) supports sustained high-end demand. The key valuation question is what portion of current AI capex intensity is structural versus a near-term buildout cycle that may moderate, since moderation would show up as lower leading-edge utilization and margin compression. Investors underwriting current valuations are implicitly taking a view on the durability of AI infrastructure spending as a percentage of global GDP.

Frequently asked questions